ARM Cortex-A76 Core User Manual

Traps and enables
For a description of the prioritization of any generated exceptions, see Exception priority order
in the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for
exceptions taken to AArch32 state, and see Synchronous exception prioritization for exceptions
taken to AArch64 state. Subject to these prioritization rules, the following traps and enables are
applicable when accessing this register.
ERXPFGCTLR_EL1 is accessible at EL3 and can be accessible at EL1 and EL2 depending on
the value of bit[5] in ACTLR_EL2 and ACTLR_EL3. See B2.6 ACTLR_EL2, Auxiliary Control
Register, EL2 on page B2-145 and B2.7 ACTLR_EL3, Auxiliary Control Register, EL3
on page B2-147.
ERXPFGCTLR_EL1 is UNDEFINED at EL0.
If ERXPFGCTLR_EL1 is accessible at EL1 and HCR_EL2.TERR == 1, then direct reads and
writes of ERXPFGCTLR_EL1 at Non-secure EL1 generate a Trap exception to EL2.
If ERXPFGCTLR_EL1 is accessible at EL1 or EL2 and SCR_EL3.TERR == 1, then direct
reads and writes of ERXPFGCTLR_EL1 at EL1 or EL2 generate a Trap exception to EL3.
B2 AArch64 system registers
B2.44 ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control Register, EL1
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B2-205
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core