ARM Cortex-A76 Core User Manual

[4:2]
Reserved, RES0.
UC, [1]
Uncontainable error generation enable. The possible values are:
0 No uncontainable error is generated.
1 An uncontainable error might be generated when the Error Generation Counter is
triggered.
[0]
Reserved, RES0.
Configurations
There are no configuration notes.
ERR0PFGCTLR resets to 0x00000000.
ERR0PFGCTLR is accessible from the following registers when ERRSELR.SEL==0:
• B2.44 ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control Register, EL1
on page B2-204.
B3 Error system registers
B3.8 ERR0PFGCTLR, Error Pseudo Fault Generation Control Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B3-304
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core