ARM Cortex-A76 Core

Table D4-2 PMU events (continued)
Bit Event mnemonic Description
[23] L2D_CACHE_REFILL
L2 Data cache refill:
1
This event is implemented.
[22] L2D_CACHE
L2 Data cache access:
1
This event is implemented.
[21] L1D_CACHE_WB
L1 Data cache Write-Back:
1
This event is implemented.
[20] L1I_CACHE
L1 Instruction cache access:
1
This event is implemented.
[19] MEM_ACCESS
Data memory access:
1
This event is implemented.
[18] BR_PRED
Predictable branch speculatively executed:
1
This event is implemented.
[17] CPU_CYCLES
Cycle:
1
This event is implemented.
[16] BR_MIS_PRED
Mispredicted or not predicted branch speculatively executed:
1
This event is implemented.
[15] UNALIGNED_LDST_RETIRED
Instruction architecturally executed, condition check pass - unaligned load or store:
0
This event is not implemented.
[14] BR_RETURN_RETIRED
Instruction architecturally executed, condition check pass - procedure return:
0
This event is not implemented.
[13] BR_IMMED_RETIRED
Instruction architecturally executed - immediate branch:
0
This event is not implemented.
[12] PC_WRITE_RETIRED
Instruction architecturally executed, condition check pass - software change of the PC:
0
This event is not implemented.
[11] CID_WRITE_RETIRED
Instruction architecturally executed, condition check pass - write to CONTEXTIDR:
1
This event is implemented.
[10] EXC_RETURN
Instruction architecturally executed, condition check pass - exception return:
1
This event is implemented.
D4 AArch32 PMU registers
D4.2 PMCEID0, Performance Monitors Common Event Identification Register 0
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