Chapter D3
Memory-mapped debug registers
This chapter describes the memory-mapped debug registers and shows examples of how to use them.
It contains the following sections:
• D3.1 Memory-mapped debug register summary on page D3-416.
• D3.2 EDCIDR0, External Debug Component Identification Register 0 on page D3-420.
• D3.3 EDCIDR1, External Debug Component Identification Register 1 on page D3-421.
• D3.4 EDCIDR2, External Debug Component Identification Register 2 on page D3-422.
• D3.5 EDCIDR3, External Debug Component Identification Register 3 on page D3-423.
• D3.6 EDDEVID, External Debug Device ID Register 0 on page D3-424.
• D3.7 EDDEVID1, External Debug Device ID Register 1 on page D3-425.
• D3.8 EDPIDR0, External Debug Peripheral Identification Register 0 on page D3-426.
• D3.9 EDPIDR1, External Debug Peripheral Identification Register 1 on page D3-427.
• D3.10 EDPIDR2, External Debug Peripheral Identification Register 2 on page D3-428.
• D3.11 EDPIDR3, External Debug Peripheral Identification Register 3 on page D3-429.
• D3.12 EDPIDR4, External Debug Peripheral Identification Register 4 on page D3-430.
• D3.13 EDPIDRn, External Debug Peripheral Identification Registers 5-7 on page D3-431.
• D3.14 EDRCR, External Debug Reserve Control Register on page D3-432.
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