ARM Cortex-A76 Core User Manual

Table D3-1 Memory-mapped debug register summary (continued)
Offset Name Type Width Description
0x408
DBGBCR0_EL1 RW 32 D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
on page D2-408
0x40C
- - - Reserved
0x410
DBGBVR1_EL1[31:0] RW 64 Debug Breakpoint Value Register 1
0x414
DBGBVR1_EL1[63:32]
0x418
DBGBCR1_EL1 RW 32 D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
on page D2-408
0x41C
- - - Reserved
0x420
DBGBVR2_EL1[31:0] RW 64 Debug Breakpoint Value Register 2
0x424
DBGBVR2_EL1[63:32]
0x428
DBGBCR2_EL1 RW 32 D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
on page D2-408
0x42C
- - - Reserved
0x430
DBGBVR3_EL1[31:0] RW 64 Debug Breakpoint Value Register 3
0x434
DBGBVR3_EL1[63:32]
0x438
DBGBCR3_EL1 RW 32 D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
on page D2-408
0x43C
- - - Reserved
0x440
DBGBVR4_EL1[31:0] RW 64 Debug Breakpoint Value Register 4
0x444
DBGBVR4_EL1[63:32]
0x448
DBGBCR4_EL1 RW 32 D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
on page D2-408
0x44C
- - - Reserved
0x450
DBGBVR5_EL1[31:0] RW 64 Debug Breakpoint Value Register 5
0x454
DBGBVR5_EL1[63:32]
0x458
DBGBCR5_EL1 RW 32 D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
on page D2-408
0x45C-0x7FC
- - - Reserved
0x800
DBGWVR0_EL1[31:0] RW 64 Debug Watchpoint Value Register 0
0x804
DBGWVR0_EL1[63:32]
0x808
DBGWCR0_EL1 RW 32 D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
on page D2-412
0x80C
- - - Reserved
0x810
DBGWVR1_EL1[31:0] RW 64 Debug Watchpoint Value Register 1
0x814
DBGWVR1_EL1[63:32]
0x818
DBGWCR1_EL1 RW 32 D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
on page D2-412
D3 Memory-mapped debug registers
D3.1 Memory-mapped debug register summary
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core