ARM Cortex-A76 Core User Manual

D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
The DBGWCRn_EL1 holds control information for a watchpoint. Each DBGWCR_EL1 is associated
with a DBGWVR_EL1 to form a Watchpoint Register Pair (WRP). DBGWCRn_EL1 is associated with
DBGWVRn_EL1 to form WRPn. The range of n for DBGBCRn_EL1 is 0 to 3.
Bit field descriptions
The DBGWCRn_EL1 registers are 32-bit registers.
BAS
31 29 28 24 23 21 20 19 16 15 14 13 12 5 4 3 2 1 0
WT
SSC LSCMASK LBN
HMC
PAC E
RES0
Figure D2-3 DBGWCRn_EL1 bit assignments
RES0, [31:29]
RES0 Reserved.
MASK, [28:24]
Address mask. Only objects up to 2GB can be watched using a single mask.
0b0000
0
No mask.
0b0000
1
Reserved.
0b0001
0
Reserved.
Other values mask the corresponding number of address bits, from 0b00011 masking 3 address
bits (0x00000007 mask for address) to 0b11111 masking 31 address bits (0x7FFFFFFF mask for
address).
RES0, [23:21]
RES0 Reserved.
WT, [20]
Watchpoint type. Possible values are:
0 Unlinked data address match.
1 Linked data address match.
On Cold reset, the field reset value is architecturally UNKNOWN.
LBN, [19:16]
Linked breakpoint number. For Linked data address watchpoints, this specifies the index of the
Context-matching breakpoint linked to.
On Cold reset, the field reset value is architecturally UNKNOWN.
SSC, [15:14]
Security state control. Determines the Security states under which a watchpoint debug event for
watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields.
On Cold reset, the field reset value is architecturally UNKNOWN.
D2 AArch64 debug registers
D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
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D2-412
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core