ARM Cortex-A76 Core User Manual

D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
The DBGBCRn_EL1 holds control information for a breakpoint. Each DBGBVR_EL1 is associated with
a DBGBCR_EL1 to form a Breakpoint Register Pair (BRP). DBGBVRn_EL1 is associated with
DBGBCRn_EL1 to form BRPn. The range of n for DBGBCRn_EL1 is 0 to 5.
Bit field descriptions
The DBGBCRn_EL1 registers are 32-bit registers.
31 24 23 20 19 16 15 13 9 8 5 4 3 2 1 0
LBN SSC
12
HMC
14
BT BAS PMC E
RES0
Figure D2-1 DBGBCRn_EL1 bit assignments
RES0, [31:24]
RES0 Reserved.
BT, [23:20]
Breakpoint Type. This field controls the behavior of Breakpoint debug event generation. This
includes the meaning of the value held in the associated DBGBVRn_EL1, indicating whether it
is an instruction address match or mismatch, or a Context match. It also controls whether the
breakpoint is linked to another breakpoint. The possible values are:
0b0000 Unlinked instruction address match.
0b0001 Linked instruction address match.
0b0010 Unlinked Context ID match.
0b0011 Linked Context ID match.
0b0100 Unlinked instruction address mismatch.
0b0101 Linked instruction address mismatch.
0b0110 Unlinked CONTEXTIDR_EL1 match.
0b0111 Linked CONTEXTIDR_EL1 match.
0b1000 Unlinked VMID match.
0b1001 Linked VMID match.
0b1010 Unlinked VMID + Conext ID match.
0b1011 Linked VMID + Context ID match.
0b1100 Unlinked CONTEXTIDR_EL2 match.
0b1101 Linked CONTEXTIDR_EL2 match.
0b1110 Unlinked Full Context ID match.
0b1111 Linked Full Context ID match.
The field break down is:
• BT[3:1]: Base type. If the breakpoint is not context-aware, these bits are RES0. Otherwise, the
possible values are:
0b000 Match address. DBGBVRn_EL1 is the address of an instruction.
0b001 Match context ID. DBGBVRn_EL1[31:0] is a context ID.
0b010 Match VMID. DBGBVRn_EL1[47:32] is a VMID.
D2 AArch64 debug registers
D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core