ARM Cortex-A76 Core User Manual

0b011 Match VMID and CONTEXTIDR_EL1. DBGBVRn_EL1[31:0] is a context ID,
and DBGBVRn_EL1[47:32] is a VMID.
• BT[2]: Mismatch. RES0.
• BT[0]: Enable linking.
LBN, [19:16]
Linked breakpoint number. For Linked address matching breakpoints, this specifies the index of
the Context-matching breakpoint linked to.
SSC, [15:14]
Security State Control. Determines the Security states under which a Breakpoint debug event for
breakpoint n is generated.
This field must be interpreted with the Higher Mode Control (HMC), and Privileged Mode
Control (PMC), fields to determine the mode and security states that can be tested.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for
possible values of the HMC and PMC fields.
HMC, [13]
Hyp Mode Control bit. Determines the debug perspective for deciding when a breakpoint debug
event for breakpoint n is generated.
This bit must be interpreted with the SSC and PMC fields to determine the mode and security
states that can be tested.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for
possible values of the SSC and PMC fields.
RES0, [12:9]
RES0 Reserved.
BAS, [8:5]
Byte Address Select. Defines which half-words a regular breakpoint matches, regardless of the
instruction set and execution state. A debugger must program this field as follows:
0x3 Match the T32 instruction at DBGBVRn_EL1.
0xC Match the T32 instruction at DBGBVRn+2_EL1.
0xF Match the A64 or A32 instruction at DBGBVRn_EL1, or context match.
All other values are reserved.
The Armv8-A architecture does not support direct execution of Java bytecodes. BAS[3] and
BAS[1] ignore writes and on reads return the values of BAS[2] and BAS[0] respectively.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more
information on how the BAS field is interpreted by hardware.
RES0, [4:3]
RES0 Reserved.
D2 AArch64 debug registers
D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
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reserved.
D2-409
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core