PMC, [2:1]
Privileged Mode Control. Determines the exception level or levels that a breakpoint debug event
for breakpoint n is generated.
This field must be interpreted with the SSC and HMC fields to determine the mode and security
states that can be tested.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for
possible values of the SSC and HMC fields.
Bits[2:1] have no effect for accesses made in Hyp mode.
E, [0]
Enable breakpoint. This bit enables the BRP:
0 BRP disabled.
1 BRP enabled.
A BRP never generates a breakpoint debug event when it is disabled.
The value of DBGBCRn_EL1.E is UNKNOWN on reset. A debugger must ensure that
DBGBCRn_EL1.E has a defined value before it enables debug.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
D2 AArch64 debug registers
D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D2-410
Non-Confidential
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