ARM Cortex-A76 Core User Manual

PMC, [2:1]
Privileged Mode Control. Determines the exception level or levels that a breakpoint debug event
for breakpoint n is generated.
This field must be interpreted with the SSC and HMC fields to determine the mode and security
states that can be tested.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for
possible values of the SSC and HMC fields.
Bits[2:1] have no effect for accesses made in Hyp mode.
E, [0]
Enable breakpoint. This bit enables the BRP:
0 BRP disabled.
1 BRP enabled.
A BRP never generates a breakpoint debug event when it is disabled.
The value of DBGBCRn_EL1.E is UNKNOWN on reset. A debugger must ensure that
DBGBCRn_EL1.E has a defined value before it enables debug.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
D2 AArch64 debug registers
D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D2-410
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core