ARM Cortex-A76 Core User Manual

Table D3-1 Memory-mapped debug register summary (continued)
Offset Name Type Width Description
0x81C
- - - Reserved
0x820
DBGWVR2_EL1[31:0] RW 64 Debug Watchpoint Value Register 2
0x824
DBGWVR2_EL1[63:32]
0x828
DBGWCR2_EL1 RW 32 D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
on page D2-412
0x82C
- - - Reserved
0x830
DBGWVR3_EL1[31:0] RW 64 Debug Watchpoint Value Register 0,
0x834
DBGWVR3_EL1[63:32]
0x838
DBGWCR3_EL1 RW 32 D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
on page D2-412
0x83C-0xCFC
- - - Reserved
0xD00
MIDR RO 32 B2.84 MIDR_EL1, Main ID Register, EL1 on page B2-266
0xD04-0xD1C
- - - Reserved
0xD20
EDPFR[31:0] RO 64 B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1
on page B2-227
0xD24
EDPFR[63:32]
0xD28
EDDFR[31:0] RO 64 B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1
on page B2-227
0xD2C
EDDFR[63:32]
0xD60-0xEFC
- - - Reserved
0xF00
- - - Reserved
0xF04-0xF9C
- - - Reserved
0xFA0
DBGCLAIMSET_EL1 RW 32 D2.3 DBGCLAIMSET_EL1, Debug Claim Tag Set Register, EL1
on page D2-411
0xFA4
DBGCLAIMCLR_EL1 RW 32 Debug Claim Tag Clear Register
0xFA8
EDDEVAFF0 RO 32
External Debug Device Affinity Register 0
0xFAC
EDDEVAFF1 RO 32 External Debug Device Affinity Register 1
0xFB0
- - -
Reserved
0xFB4
- - - Reserved
0xFB8
DBGAUTHSTATUS_EL1 RO 32
Debug Authentication Status Register
0xFBC
EDDEVARCH RO 32 External Debug Device Architecture Register
0xFC0
EDDEVID2 RO 32 External Debug Device ID Register 2, RES0
0xFC4
EDDEVID1 RO 32 D3.7 EDDEVID1, External Debug Device ID Register 1 on page D3-425
0xFC8
EDDEVID RO 32 D3.6 EDDEVID, External Debug Device ID Register 0 on page D3-424
0xFCC
EDDEVTYPE RO 32
External Debug Device Type Register
0xFD0
EDPIDR4 RO 32 D3.12 EDPIDR4, External Debug Peripheral Identification Register 4
on page D3-430
D3 Memory-mapped debug registers
D3.1 Memory-mapped debug register summary
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
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D3-418
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core