ARM Cortex-A76 Core

Table D3-1 Memory-mapped debug register summary (continued)
Offset Name Type Width Description
0xFD4-0xFDC
EDPIDR5-7 RO 32 D3.13 EDPIDRn, External Debug Peripheral Identification Registers
5-7 on page D3-431
0xFE0
EDPIDR0 RO 32 D3.8 EDPIDR0, External Debug Peripheral Identification Register 0
on page D3-426
0xFE4
EDPIDR1 RO 32 D3.9 EDPIDR1, External Debug Peripheral Identification Register 1
on page D3-427
0xFE8
EDPIDR2 RO 32 D3.10 EDPIDR2, External Debug Peripheral Identification Register 2
on page D3-428
0xFEC
EDPIDR3 RO 32 D3.11 EDPIDR3, External Debug Peripheral Identification Register 3
on page D3-429
0xFF0
EDCIDR0 RO 32 D3.2 EDCIDR0, External Debug Component Identification Register 0
on page D3-420
0xFF4
EDCIDR1 RO 32 D3.3 EDCIDR1, External Debug Component Identification Register 1
on page D3-421
0xFF8
EDCIDR2 RO 32 D3.4 EDCIDR2, External Debug Component Identification Register 2
on page D3-422
0xFFC
EDCIDR3 RO 32 D3.5 EDCIDR3, External Debug Component Identification Register 3
on page D3-423
D3 Memory-mapped debug registers
D3.1 Memory-mapped debug register summary
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