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0x4 • Support for shifts of loads and stores over the range LSL 0-3.

• Support for other constant shift options, both on load/store and other instructions.

• Support for register-controlled shift options.

Unpriv, [3:0]

Indicates the implemented unprivileged instructions.

0x2 • The LDRBT, LDRT, STRBT, and STRT instructions.

• The LDRHT, LDRSBT, LDRSHT, and STRHT instructions.

Configurations

In an AArch64-only implementation, this register is UNKNOWN.

Must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1,

ID_ISAR5_EL1, and ID_ISAR6_EL1. See:

• B2.65 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1 on page B2-233.

• B2.66 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1 on page B2-235.

• B2.67 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1 on page B2-237.

• B2.68 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1 on page B2-239.

• B2.70 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1 on page B2-243.

• B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1 on page B2-245.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm

Architecture Reference Manual Armv8, for Armv8-A architecture profile.

B2 AArch64 system registers

B2.69 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1

reserved.

B2-242

Non-Confidential

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