0x3 • The SSAT and USAT instructions, and the Q bit in the PSRs.
• The PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8,
SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16,
SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX,
UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX,
USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, UXTB16 instructions, and
the GE[3:0] bits in the PSRs.
The SIMD field relates only to implemented instructions that perform SIMD
operations on the general-purpose registers. In an implementation that supports
Advanced SIMD and floating-point instructions, MVFR0, MVFR1, and MVFR2 give
information about the implemented Advanced SIMD instructions.
Saturate, [3:0]
Indicates the implemented Saturate instructions:
0x1 The QADD, QDADD, QDSUB, QSUB Q bit in the PSRs.
Configurations
In an AArch64-only implementation, this register is UNKNOWN.
Must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR4_EL1,
ID_ISAR5_EL1, and ID_ISAR6_EL1. See:
• B2.65 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1 on page B2-233.
• B2.66 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1 on page B2-235.
• B2.67 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1 on page B2-237.
• B2.69 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1 on page B2-241.
• B2.70 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1 on page B2-243.
• B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1 on page B2-245.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.68 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-240
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