ARM Cortex-A76 Core User Manual

Export enable. This bit permits events to be exported to another debug device, such as a trace
macrocell, over an event bus. The possible values are:
0b0 Export of events is disabled. This is the reset value.
0b1 Export of events is enabled.
No events are exported when counting is prohibited.
This field does not affect the generation of Performance Monitors overflow interrupt requests or
signaling to a cross-trigger interface (CTI) that can be implemented as signals exported from the
PE.
When this register has an architecturally defined reset value, if this field is implemented as an
RW field, it resets to 0.
D, [3]
Clock divider. The possible values are:
0b0 When enabled, counter CCNT counts every clock cycle. This is the reset value.
0b1 When enabled, counter CCNT counts once every 64 clock cycles.
Arm deprecates use of PMCR.D = 0b1.
C, [2]
Cycle counter reset. This bit is WO. The effects of writing to this bit are:
0b0 No action. This is the reset value.
0b1 Reset PMCCNTR to zero.
This bit is always RAZ.
Resetting PMCCNTR does not clear the PMCCNTR overflow bit to 0. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.
P, [1]
Event counter reset. This bit is WO. The effects of writing to this bit are:
0b0 No action. This is the reset value.
0b1 Reset all event counters accessible in the current EL, not including PMCCNTR, to
zero.
This bit is always RAZ.
In Non-secure EL0 and EL1, a write of 1 to this bit does not reset event counters that
HDCR.HPMN or MDCR_EL2.HPMN reserves for EL2 use.
In EL2 and EL3, a write of 1 to this bit resets all the event counters.
Resetting the event counters does not clear any overflow bits to 0.
E, [0]
Enable. The possible values are:
0b0 All counters that are accessible at Non-secure EL1, including PMCCNTR, are
disabled. This is the reset value.
0b1 When this register has an architecturally defined reset value, this field resets to 0.
This bit is RW.
This bit does not affect the operation of event counters that HDCR.HPMN or
MDCR_EL2.HPMN reserves for EL2 use.
When this register has an architecturally defined reset value, this field resets to 0.
D4 AArch32 PMU registers
D4.4 PMCR, Performance Monitors Control Register
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core