ARM Cortex-A76 Core User Manual

Configurations
AArch32 System register PMCR is architecturally mapped to AArch64 System register
PMCR_EL0. See D5.4 PMCR_EL0, Performance Monitors Control Register, EL0
on page D5-453.
AArch32 System register PMCR bits [6:0] are architecturally mapped to External register
PMCR_EL0[6:0].
There is one instance of this register that is used in both Secure and Non-secure states.
This register is in the Warm reset domain. Some or all RW fields of this register have defined
reset values. On a Warm or Cold reset these apply only if the PE resets into an Exception level
that is using AArch32. Otherwise, on a Warm or Cold reset RW fields in this register reset to
architecturally UNKNOWN values.
D4 AArch32 PMU registers
D4.4 PMCR, Performance Monitors Control Register
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D4-443
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core