ARM Cortex-A76 Core User Manual

UC, [1]
Uncontainable Error generation. The value is:
1 This feature is controllable.
[0]
RES0 Reserved.
Configurations
There are no configuration notes.
ERR0PFGFR resets to 0xC0000062.
When ERRSELR.SEL==0, ERR0PFGFR is accessible from B2.45 ERXPFGFR_EL1, Selected
Pseudo Fault Generation Feature Register, EL1 on page B2-206.
B3 Error system registers
B3.9 ERR0PFGFR, Error Pseudo Fault Generation Feature Register
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B3-306
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core