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ARM Cortex-A76 Core - Page 320

ARM Cortex-A76 Core
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0 Disables use of ICC_PMR as a hint for interrupt distribution.
1 Enables use of ICC_PMR as a hint for interrupt distribution.
RES0, [5:2]
Reserved, RES0.
EOImode, [1]
End of interrupt mode for the current security state. The possible values are:
0 ICC_EOIR0 and ICC_EOIR1 provide both priority drop and interrupt deactivation
functionality. Accesses to ICC_DIR are UNPREDICTABLE.
1 ICC_EOIR0 and ICC_EOIR1 provide priority drop functionality only. ICC_DIR
provides interrupt deactivation functionality.
CBPR, [0]
Common Binary Point Register. Control whether the same register is used for interrupt
preemption of both Group 0 and Group 1 interrupt. The possible values are:
0 ICC_BPR0 determines the preemption group for Group 0 interrupts.
ICC_BPR1 determines the preemption group for Group 1 interrupts.
1 ICC_BPR0 determines the preemption group for Group 0 and Group 1 interrupts.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm
®
Generic Interrupt Controller Architecture Specification.
B4 GIC registers
B4.7 ICC_CTLR_EL1, Interrupt Controller Control Register, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B4-320
Non-Confidential

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