ARM Cortex-A76 Core User Manual

Virtual Common Binary Point Register. The possible values are:
0x0 ICV_BPR0_EL1 determines the preemption group for virtual Group 0 interrupts
only.
ICV_BPR1_EL1 determines the preemption group for virtual Group 1 interrupts.
0x1 ICV_BPR0_EL1 determines the preemption group for both virtual Group 0 and
virtual Group 1 interrupts.
Reads of ICV_BPR1_EL1 return ICV_BPR0_EL1 plus one, saturated to 111. Writes
to ICV_BPR1_EL1 are IGNORED.
VFIQEn, [3]
Virtual FIQ enable. The value is:
0x1 Group 0 virtual interrupts are presented as virtual FIQs.
RES0, [2]
Reserved, RES0.
VENG1, [1]
Virtual Group 1 interrupt enable. The possible values are:
0x0 Virtual Group 1 interrupts are disabled.
0x1 Virtual Group 1 interrupts are enabled.
VENG0, [0]
Virtual Group 0 interrupt enable. The possible values are:
0x0 Virtual Group 0 interrupts are disabled.
0x1 Virtual Group 0 interrupts are enabled.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm
®
Generic Interrupt Controller Architecture Specification.
B4 GIC registers
B4.22 ICH_VMCR_EL2, Interrupt Controller Virtual Machine Control Register, EL2
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B4-342
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core