ARM Cortex-A76 Core User Manual

1 Enables max-power throttling mechanism.
Note
Both the MXP_EN bit and the MPMMEN input pin at the DSU cluster level must be
asserted to enable the max-power throttling mechanism.
RES0, [60:59]
RES0 Reserved.
MXP_TP, [58:57]
Percentage of throttling in the Load-Store and Vector Execute units during the period when
throttling has been triggered and is active. The possible values are:
00 Throttle by 60%. This is the reset value.
01 Throttle by 50%.
10 Throttle by 40%.
11 Throttle by 30%.
MXP_ATHR, [56:55]
Peak activity threshold at which max-power throttling is triggered. The possible values are:
00 Max-power throttling triggered at 70% of peak activity. This is the reset value.
01 Max-power throttling triggered at 60% of peak activity.
10 Max-power throttling triggered at 50% of peak activity.
11 Max-power throttling triggered at 40% of peak activity.
MM_VMID_THR, [54]
VMID filter threshold. The possible values are:
0 Flush VMID filter after 16 unique VMID allocations to the MMU Translation Cache.
This is the reset value.
1 Flush VMID filter after 32 unique VMID allocations to the MMU Translation Cache.
MM_ASP_EN, [53]
Disables allocation of splintered pages in L2 TLB. The possible values are:
0 Enables allocation of splintered pages in the L2 TLB. This is the reset value.
1 Disables allocation of splintered pages in the L2 TLB.
MM_CH_DIS, [52]
Disables use of contiguous hint. The possible values are:
0 Enables use of contiguous hint. This is the reset value.
1 Disables use of contiguous hint.
MM_TLBPF_DIS, [51]
Disables L2 TLB prefetcher. The possible values are:
0 Enables L2 TLB prefetcher. This is the reset value.
1 Disables L2 TLB prefetcher.
HPA_MODE, [50:49]
Hardware Page Aggregation (HPA) mode. The possible values are:
B2 AArch64 system registers
B2.26 CPUECTLR_EL1, CPU Extended Control Register, EL1
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B2-173
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core