ARM Cortex-A76 Core User Manual

00 Moderately conservative hardware page aggregation. This is the reset value.
01 Aggressive hardware page aggregation.
10 Moderately aggressive hardware page aggregation.
11 Conservative hardware page aggregation.
HPA_CAP, [48]
Limited or full hardware page aggregation selection . The possible values are:
0 Limited hardware page aggregation. This is the reset value.
1 Full hardware page aggregation.
HPA_L1_DIS, [47]
Disables HPA in L1 TLBs (but continues to use HPA in L2 TLB). The possible values are:
0 Enables hardware page aggregation in L1 TLBs. This is the reset value.
1 Disables hardware page aggregation in L1 TLBs.
HPA_DIS, [46]
Disables hardware page aggregation. The possible values are:
0 Enables hardware page aggregation. This is the reset value.
1 Disables hardware page aggregation.
RES0, [45:44]
RES0 Reserved.
L2_FLUSH, [43]
Allocation behavior of copybacks caused by L2 cache hardware flush and DC CISW
instructions targeting the L2 cache. If it is known that data is likely to be used soon by another
core, setting this bit can improve system performance. The possible values are:
0 L2 cache flushes and invalidates by set/way do not allocate in the L3 cache. Cache
lines in the UniqueDirty state cause WriteBack transactions with the allocation hint
cleared, while cache lines in UniqueClean or SharedClean states cause address-only
Evict transactions. This is the reset value.
1 L2 cache flushes by set/way allocate in the L3 cache. Cache lines in the UniqueDirty
or UniqueClean state cause WriteBackFull or WriteEvictFull transactions,
respectively, both with the allocation hint set. Cache lines in the SharedClean state
cause address-only Evict transactions.
RES0, [42]
RES0 Reserved.
PFT_MM, [41:40]
DRAM prefetch using PrefetchTgt transactions for table walk requests. The possible values are:
00 Disable prefetchtgt generation for requests from the Memory Management unit
(MMU). This is the reset value.
01 Conservatively generate prefetchtgt for cacheable requests from the MMU, always
generate for non-cacheable.
10 Aggressively generate prefetchtgt for cacheable requests from the MMU, always
generate for non-cacheable.
11 Always generate prefetchtgt for cacheable requests from the MMU, always generate
for non-cacheable.
B2 AArch64 system registers
B2.26 CPUECTLR_EL1, CPU Extended Control Register, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-174
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core