ARM Cortex-A76 Core User Manual

PFT_LS, [39:38]
DRAM prefetch using PrefetchTgt transactions for load and store requests. The possible values
are:
00 Disable prefetchtgt generation for requests from the Load-Store unit (LS). This is the
reset value.
01 Conservatively generate prefetchtgt for cacheable requests from the LS, always
generate for non-cacheable.
10 Aggressively generate prefetchtgt for cacheable requests from the LS, always generate
for non-cacheable.
11 Always generate prefetchtgt for cacheable requests from the LS, always generate for
non-cacheable.
PFT_IF, [37:36]
DRAM prefetch using PrefetchTgt transactions for instruction fetch requests. The possible
values are:
00 Disable prefetchtgt generation for requests from the Instruction Fetch unit (IF). This is
the reset value.
01 Conservatively generate prefetchtgt for cacheable requests from the IF, always
generate for non-cacheable.
10 Aggressively generate prefetchtgt for cacheable requests from the IF, always generate
for non-cacheable.
11 Always generate prefetchtgt for cacheable requests from the IF, always generate for
non-cacheable.
CA_UCLEAN_EVICT_EN, [35]
Enables sending WriteEvict transactions on the CPU CHI interface for UniqueClean evictions.
WriteEvict transactions update downstream caches. Enable WriteEvict transactions only if there
is an additional level of cache below the CPU's Level 2 cache. The possible values are:
0 Disables sending data with UniqueClean evictions.
1 Enables sending data with UniqueClean evictions. This is the reset value.
CA_EVICT_DIS, [34]
Disables sending of Evict transactions on the CPU CHI interface for clean cache lines that are
evicted from the core. Evict transactions are required only if the system contains a snoop filter
that requires notification when the core evicts the cache line. The possible values are:
0 Enables sending Evict transactions. This is the reset value.
1 Disables sending Evict transactions.
RES0, [33]
RES0 Reserved.
ATOMIC_ACQ_NEAR, [32]
An atomic instruction to WB memory with acquire semantics that does not hit in the cache in
Exclusive state, may make up to one fill request. The possible values are:
0 Acquire-atomic is near if cache line is already Exclusive, otherwise make far atomic
request.
1 Acquire-atomic will make up to 1 fill request to perform near. This is the reset value.
ATOMIC_ST_NEAR, [31]
B2 AArch64 system registers
B2.26 CPUECTLR_EL1, CPU Extended Control Register, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-175
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core