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0x0 No support. This means the LDM and STM instructions are not interruptible.

MemHint, [7:4]

Indicates the implemented memory hint instructions:

0x4 The PLD, PLI, and PLDWinstructions.

LoadStore, [3:0]

Indicates the implemented additional load/store instructions:

0x2 The LDRD and STRD instructions.

The Load Acquire (LDAB, LDAH, LDA, LDAEXB, LDAEXH, LDAEX, and LDAEXD) and Store

Release (STLB, STLH, STL, STLEXB, STLEXH, STLEX, and STLEXD) instructions.

Configurations

In an AArch64-only implementation, this register is UNKNOWN.

Must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1,

ID_ISAR5_EL1, and ID_ISAR6_EL1. See:

• B2.65 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1 on page B2-233.

• B2.66 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1 on page B2-235.

• B2.68 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1 on page B2-239.

• B2.69 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1 on page B2-241.

• B2.70 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1 on page B2-243.

• B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1 on page B2-245.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm

Architecture Reference Manual Armv8, for Armv8-A architecture profile.

B2 AArch64 system registers

B2.67 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1

reserved.

B2-238

Non-Confidential

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ARM Cortex-A76 Core Specifications

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