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0x0 No SHA2 instructions are implemented. This is the value if the core implementation

does not include the Cryptographic Extension.

0x1 SHA256H, SHA256H2, SHA256U0, and SHA256U1 implemented. This is the value if the

core implementation includes the Cryptographic Extension.

SHA1, [11:8]

Indicates whether SHA1 instructions are implemented. The possible values are:

0x0 No SHA1 instructions implemented. This is the value if the core implementation does

not include the Cryptographic Extension.

0x1 SHA1C, SHA1P, SHA1M, SHA1SU0, and SHA1SU1 implemented. This is the value if the

core implementation includes the Cryptographic Extension.

AES, [7:4]

Indicates whether AES instructions are implemented. The possible values are:

0x0 No AES instructions implemented. This is the value if the core implementation does

not include the Cryptographic Extension.

0x2 AESE, AESD, AESMC, and AESIMC implemented, plus PMULL and PMULL2 instructions

operating on 64-bit data. This is the value if the core implementation includes the

Cryptographic Extension.

[3:0]

Reserved, RES0.

Configurations

ID_AA64ISAR0_EL1 is architecturally mapped to external register ID_AA64ISAR0.

Bit fields and details that are not provided in this description are architecturally defined. See the

Arm

Architecture Reference Manual Armv8, for Armv8-A architecture profile.

B2 AArch64 system registers

B2.56 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1

reserved.

B2-220

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ARM Cortex-A76 Core Specifications

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