ARM Cortex-A76 Core User Manual

B4.3 ICC_AP0R0_EL1, Interrupt Controller Active Priorities Group 0 Register 0,
EL1
The ICC_AP0R0_EL1 provides information about Group 0 active priorities.
Bit descriptions
This register is a 32-bit register and is part of:
• The GIC system registers functional group.
• The GIC control registers functional group.
The core implements 5 bits of priority with 32 priority levels, corresponding to the 32 bits [31:0] of the
register. The possible values for each bit are:
0x00000000 No interrupt active. This is the reset value.
0x00000001 Interrupt active for priority 0x0.
0x00000002 Interrupt active for priority 0x8.
...
0x80000000 Interrupt active for priority 0xF8.
Details not provided in this description are architecturally defined. See the Arm
®
Generic Interrupt
Controller Architecture Specification.
B4 GIC registers
B4.3 ICC_AP0R0_EL1, Interrupt Controller Active Priorities Group 0 Register 0, EL1
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B4-315
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core