ARM Cortex-A76 Core User Manual

Chapter C2
Performance Monitor Unit
This chapter describes the Performance Monitor Unit (PMU) and the registers that it uses.
It contains the following sections:
• C2.1 About the PMU on page C2-372.
• C2.2 PMU functional description on page C2-373.
• C2.3 PMU events on page C2-374.
• C2.4 PMU interrupts on page C2-383.
• C2.5 Exporting PMU events on page C2-384.
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C2-371
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core