ARM Cortex-A76 Core

0x4 Maximum of 32-bit Context ID size.
IASIZE, [4:0]
Instruction address size in bytes:
0x8 Maximum of 64-bit address size.
Bit fields and details not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCIDR2 can be accessed through the external debug interface, offset 0x1E8.
D9 ETM registers
D9.31 TRCIDR2, ID Register 2
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D9-538
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