RES0 Reserved.
PWREN, [7]
Power Control Registers enable. The possible values are:
0 Registers CPUPWRCTLR, CLUSTERPWRCTLR, CLUSTERPWRDN,
CLUSTERPWRSTAT, CLUSTERL3HIT and CLUSTERL3MISS are not write-
accessible from EL2 and EL1 Secure. This is the reset value.
1 Registers CPUPWRCTLR, CLUSTERPWRCTLR, CLUSTERPWRDN,
CLUSTERPWRSTAT, CLUSTERL3HIT and CLUSTERL3MISS are write-accessible
from EL2 and EL1 Secure.
RES0, [6]
RES0 Reserved.
ERXPFGEN, [5]
Error Record Registers enable. The possible values are:
0 ERXPFG* are not write-accessible from EL2 and EL1 Secure. This is the reset value.
1 ERXPFG* are write-accessible from EL2 and EL1 Secure.
AMEN, [4]
Activity Monitor enable. The possible values are:
0 Accesses from EL2, EL1 and EL0 to activity monitor registers are trapped to EL3.
1 Accesses from EL2, EL1 and EL0 to activity monitor registers are not trapped to EL2.
RES0, [3:2]
RES0 Reserved.
ECTLREN, [1]
Extended Control Registers enable. The possible values are:
0 CPUECTLR and CLUSTERECTLR are not write-accessible from EL2 and EL1
Secure. This is the reset value.
1 CPUECTLR and CLUSTERECTLR are write-accessible from EL2 and EL1 Secure.
Configurations
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.7 ACTLR_EL3, Auxiliary Control Register, EL3
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-148
Non-Confidential
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