Chapter D6
Memory-mapped PMU registers
This chapter describes the memory-mapped PMU registers and shows examples of how to use them.
It contains the following sections:
• D6.1 Memory-mapped PMU register summary on page D6-456.
• D6.2 PMCFGR, Performance Monitors Configuration Register on page D6-460.
• D6.3 PMCIDR0, Performance Monitors Component Identification Register 0 on page D6-461.
• D6.4 PMCIDR1, Performance Monitors Component Identification Register 1 on page D6-462.
• D6.5 PMCIDR2, Performance Monitors Component Identification Register 2 on page D6-463.
• D6.6 PMCIDR3, Performance Monitors Component Identification Register 3 on page D6-464.
• D6.7 PMPIDR0, Performance Monitors Peripheral Identification Register 0 on page D6-465.
• D6.8 PMPIDR1, Performance Monitors Peripheral Identification Register 1 on page D6-466.
• D6.9 PMPIDR2, Performance Monitors Peripheral Identification Register 2 on page D6-467.
• D6.10 PMPIDR3, Performance Monitors Peripheral Identification Register 3 on page D6-468.
• D6.11 PMPIDR4, Performance Monitors Peripheral Identification Register 4 on page D6-469.
• D6.12 PMPIDRn, Performance Monitors Peripheral Identification Register 5-7 on page D6-470.
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