ARM Cortex-A76 Core User Manual

0 Export of events is disabled. This is the reset value.
1 Export of events is enabled.
This bit is read/write and does not affect the generation of Performance Monitors interrupts on
the nPMUIRQ pin.
D, [3]
Clock divider:
0 When enabled, PMCCNTR_EL0 counts every clock cycle. This is the reset value.
1 When enabled, PMCCNTR_EL0 counts every 64 clock cycles.
This bit is read/write.
C, [2]
Clock counter reset. This bit is WO. The effects of writing to this bit are:
0 No action. This is the reset value.
1 Reset PMCCNTR_EL0 to 0.
This bit is always RAZ.
Resetting PMCCNTR_EL0 does not clear the PMCCNTR_EL0 overflow bit to 0. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.
P, [1]
Event counter reset. This bit is WO. The effects of writing to this bit are:
0 No action. This is the reset value.
1 Reset all event counters, not including PMCCNTR_EL0, to zero.
This bit is always RAZ.
In Non-secure EL0 and EL1, a write of 1 to this bit does not reset event counters that
MDCR_EL2.HPMN reserves for EL2 use.
In EL2 and EL3, a write of 1 to this bit resets all the event counters.
Resetting the event counters does not clear any overflow bits to 0.
E, [0]
Enable. The possible values of this bit are:
0 All counters, including PMCCNTR_EL0, are disabled. This is the reset value.
1 All counters are enabled.
This bit is RW.
In Non-secure EL0 and EL1, this bit does not affect the operation of event counters that
MDCR_EL2.HPMN reserves for EL2 use.
On Warm reset, the field resets to 0.
Configurations
AArch64 System register PMCR_EL0 is architecturally mapped to AArch32 System register
PMCR.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
D5 AArch64 PMU registers
D5.4 PMCR_EL0, Performance Monitors Control Register, EL0
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core