ARM Cortex-A76 Core User Manual

Chapter B4
GIC registers
This chapter describes the GIC registers.
It contains the following sections:
• B4.1 CPU interface registers on page B4-313.
• B4.2 AArch64 physical GIC CPU interface system register summary on page B4-314.
• B4.3 ICC_AP0R0_EL1, Interrupt Controller Active Priorities Group 0 Register 0, EL1
on page B4-315.
• B4.4 ICC_AP1R0_EL1, Interrupt Controller Active Priorities Group 1 Register 0 EL1
on page B4-316.
• B4.5 ICC_BPR0_EL1, Interrupt Controller Binary Point Register 0, EL1 on page B4-317.
• B4.6 ICC_BPR1_EL1, Interrupt Controller Binary Point Register 1, EL1 on page B4-318.
• B4.7 ICC_CTLR_EL1, Interrupt Controller Control Register, EL1 on page B4-319.
• B4.8 ICC_CTLR_EL3, Interrupt Controller Control Register, EL3 on page B4-321.
• B4.9 ICC_SRE_EL1, Interrupt Controller System Register Enable Register, EL1 on page B4-323.
• B4.10 ICC_SRE_EL2, Interrupt Controller System Register Enable register, EL2 on page B4-324.
• B4.11 ICC_SRE_EL3, Interrupt Controller System Register Enable register, EL3 on page B4-326.
• B4.12 AArch64 virtual GIC CPU interface register summary on page B4-328.
• B4.13 ICV_AP0R0_EL1, Interrupt Controller Virtual Active Priorities Group 0 Register 0, EL1
on page B4-329.
• B4.14 ICV_AP1R0_EL1, Interrupt Controller Virtual Active Priorities Group 1 Register 0, EL1
on page B4-330.
• B4.15 ICV_BPR0_EL1, Interrupt Controller Virtual Binary Point Register 0, EL1 on page B4-331.
• B4.16 ICV_BPR1_EL1, Interrupt Controller Virtual Binary Point Register 1, EL1 on page B4-332.
• B4.17 ICV_CTLR_EL1, Interrupt Controller Virtual Control Register, EL1 on page B4-333.
• B4.18 AArch64 virtual interface control system register summary on page B4-335.
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core