ARM Cortex-A76 Core User Manual

Chapter D7
PMU snapshot registers
PMU snapshot registers are an IMPLEMENTATION DEFINED extension to an Armv8-A compliant PMU to
support an external core monitor that connects to a system profiler.
It contains the following sections:
• D7.1 PMU snapshot register summary on page D7-472.
• D7.2 PMPCSSR, Snapshot Program Counter Sample Register on page D7-473.
• D7.3 PMCIDSSR, Snapshot CONTEXTIDR_EL1 Sample Register on page D7-474.
• D7.4 PMCID2SSR, Snapshot CONTEXTIDR_EL2 Sample Register on page D7-475.
• D7.5 PMSSSR, PMU Snapshot Status Register on page D7-476.
• D7.6 PMOVSSR, PMU Overflow Status Snapshot Register on page D7-477.
• D7.7 PMCCNTSR, PMU Cycle Counter Snapshot Register on page D7-478.
• D7.8 PMEVCNTSRn, PMU Cycle Counter Snapshot Registers 0-5 on page D7-479.
• D7.9 PMSSCR, PMU Snapshot Capture Register on page D7-480.
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core