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ARM Cortex-A76 Core User Manual

ARM Cortex-A76 Core
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C1.1 About debug methods
The core is part of a debug system and supports both self-hosted and external debug.
The following figure shows a typical external debug system.
Debug target
Protocol
converter
Debug host
Core
Debug
unit
Figure C1-1 External debug system
Debug host
A computer, for example a personal computer, that is running a software debugger such as the
DS-5 Debugger. With the debug host, you can issue high-level commands, such as setting a
breakpoint at a certain location or examining the contents of a memory address.
Protocol converter
The debug host sends messages to the debug target using an interface such as Ethernet.
However, the debug target typically implements a different interface protocol. A device such as
DSTREAM is required to convert between the two protocols.
Debug target
The lowest level of the system implements system support for the protocol converter to access
the debug unit using the Advanced Peripheral Bus (APB) slave interface. An example of a
debug target is a development system with a test chip or a silicon part with a core.
Debug unit
Helps debugging software that is running on the core:
• Hardware systems that are based on the core.
• Operating systems.
• Application software.
With the debug unit, you can:
• Stop program execution.
• Examine and alter process and coprocessor state.
• Examine and alter memory and the state of the input or output peripherals.
• Restart the core.
For self-hosted debug, the debug target runs additional debug monitor software that runs on the
Cortex-A76 core itself. This way, it does not require expensive interface hardware to connect a second
host computer.
C1 Debug
C1.1 About debug methods
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
C1-366
Non-Confidential

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ARM Cortex-A76 Core Specifications

General IconGeneral
ArchitectureARMv8.2-A
MicroarchitectureCortex-A76
Pipeline Depth13 stages
FrequencyUp to 3.0 GHz
Process Technology7nm
Core TypeOut-of-order
NEONYes
Power EfficiencyImproved over Cortex-A75
Performance Improvement35% over Cortex-A75
Core Count1-4 cores per cluster
ISA SupportAArch64 and AArch32
Branch PredictionYes
L1 Data Cache32KB, per core
L2 Cache256KB or 512KB, per core
L3 CacheUp to 4MB
Memory SupportLPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)DynamIQ Shared Unit (DSU)
Cryptography ExtensionsYes
Virtualization SupportYes
L1 Cache64 KB per core

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