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Selects whether a system error exception must always be traced:

0 System error exception is traced only if the instruction or exception immediately

before the system error exception is traced.

1 System error exception is always traced regardless of the value of ViewInst.

TRCRESET, [10]

Selects whether a reset exception must always be traced:

0 Reset exception is traced only if the instruction or exception immediately before the

reset exception is traced.

1 Reset exception is always traced regardless of the value of ViewInst.

SSSTATUS, [9]

Indicates the current status of the start/stop logic:

0 Start/stop logic is in the stopped state.

1 Start/stop logic is in the started state.

RES0, [8]

RES0 Reserved.

TYPE, [7]

Selects the resource type for the viewinst event:

0 Single selected resource.

1 Boolean combined resource pair.

RES0, [6:4]

RES0 Reserved.

SEL, [3:0]

Selects the resource number to use for the viewinst event, based on the value of TYPE:

When TYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].

When TYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].

Bit fields and details not provided in this description are architecturally defined. See the Arm

Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The TRCVICTLR can be accessed through the external debug interface, offset 0x080.

D9 ETM registers

D9.72 TRCVICTLR, ViewInst Main Control Register

reserved.

D9-584

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