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Indicates whether AES instructions are implemented in AArch32 state. The possible values are:

0x0 No AES instructions implemented. This is the value when the Cryptographic

Extensions are not implemented or are disabled.

0x2 • AESE, AESD, AESMC, and AESIMC implemented.

• PMULL and PMULL2 instructions operating on 64-bit data.

This is the value when the Cryptographic Extensions are implemented and enabled.

SEVL, [3:0]

Indicates whether the SEVL instruction is implemented:

0x1 SEVL implemented to send event local.

Configurations

ID_ISAR5 must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1,

ID_ISAR3_EL1, ID_ISAR4_EL1, and ID_ISAR6_EL1. See:

• B2.65 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1 on page B2-233.

• B2.66 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1 on page B2-235.

• B2.67 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1 on page B2-237.

• B2.68 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1 on page B2-239.

• B2.69 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1 on page B2-241.

• B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1 on page B2-245.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm

Architecture Reference Manual Armv8, for Armv8-A architecture profile.

B2 AArch64 system registers

B2.70 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1

reserved.

B2-244

Non-Confidential

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