ARM Cortex-A76 Core

L1Ip, [15:14]
Instruction cache policy. Indicates the indexing and tagging policy for the L1 Instruction cache:
11 Physically Indexed Physically Tagged (PIPT).
RES0, [13:4]
RES0 Reserved.
IminLine, [3:0]
Log
2
of the number of words in the smallest cache line of all the instruction caches that the core
controls.
0100 Smallest instruction cache line size is 16 words.
Configurations
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
B2 AArch64 system registers
B2.33 CTR_EL0, Cache Type Register, EL0
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-192
Non-Confidential