Table B2-1 Registers with implementation defined bit fields (continued)
Name Op0 CRn Op1 CRm Op2 Width Description
CLIDR_EL1 3 c0 1 c0 1 64 B2.19 CLIDR_EL1, Cache Level ID Register, EL1
on page B2-161
CPACR_EL1 3 c1 0 c0 2 32 B2.20 CPACR_EL1, Architectural Feature Access Control
Register, EL1 on page B2-163
CPTR_EL2 3 c1 4 c1 2 32 B2.21 CPTR_EL2, Architectural Feature Trap Register, EL2
on page B2-164
CPTR_EL3 3 c1 6 c1 2 32 B2.22 CPTR_EL3, Architectural Feature Trap Register, EL3
on page B2-165
CSSELR_EL1 3 c0 2 c0 0 32 B2.32 CSSELR_EL1, Cache Size Selection Register, EL1
on page B2-190
CTR_EL0 3 c0 3 c0 1 32 B2.33 CTR_EL0, Cache Type Register, EL0 on page B2-191
DISR_EL1 3 c12 0 c1 1 64 B2.35 DISR_EL1, Deferred Interrupt Status Register, EL1
on page B2-194
ERRIDR_EL1 3 c5 0 c3 0 32 B2.36 ERRIDR_EL1, Error ID Register, EL1 on page B2-196
ERRSELR_EL1 3 c5 0 c3 1 32 B2.37 ERRSELR_EL1, Error Record Select Register, EL1
on page B2-197
ERXADDR_EL1 3 c5 0 c4 3 64 B2.38 ERXADDR_EL1, Selected Error Record Address Register,
EL1 on page B2-198
ERXCTLR_EL1 3 c5 0 c4 1 64 B2.39 ERXCTLR_EL1, Selected Error Record Control Register,
EL1 on page B2-199
ERXFR_EL1 3 c5 0 c4 0 64 B2.40 ERXFR_EL1, Selected Error Record Feature Register, EL1
on page B2-200
ERXMISC0_EL1 3 c5 0 c5 0 64 B2.41 ERXMISC0_EL1, Selected Error Record Miscellaneous
Register 0, EL1 on page B2-201
ERXMISC1_EL1 3 c5 0 c5 1 64 B2.42 ERXMISC1_EL1, Selected Error Record Miscellaneous
Register 1, EL1 on page B2-202
ERXSTATUS_EL1 3 c5 0 c4 2 32 B2.46 ERXSTATUS_EL1, Selected Error Record Primary Status
Register, EL1 on page B2-207
ESR_EL1 3 c5 0 c2 0 32 B2.47 ESR_EL1, Exception Syndrome Register, EL1
on page B2-208
ESR_EL2 3 c5 4 c2 0 32 B2.48 ESR_EL2, Exception Syndrome Register, EL2
on page B2-209
ESR_EL3 3 c5 6 c2 0 32 B2.49 ESR_EL3, Exception Syndrome Register, EL3
on page B2-210
HACR_EL2 3 c1 4 c1 7 32 B2.50 HACR_EL2, Hyp Auxiliary Configuration Register, EL2
on page B2-211
HCR_EL2 3 c1 4 c1 0 64 B2.51 HCR_EL2, Hypervisor Configuration Register, EL2
on page B2-212
ID_AFR0_EL1 3 c0 0 c1 3 32 B2.63 ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0,
EL1 on page B2-230
B2 AArch64 system registers
B2.2 AArch64 architectural system register summary
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-128
Non-Confidential
To Next Page
Loading...
