Table B2-1 Registers with implementation defined bit fields (continued)
Name Op0 CRn Op1 CRm Op2 Width Description
ID_DFR0_EL1 3 c0 0 c1 2 32 B2.64 ID_DFR0_EL1, AArch32 Debug Feature Register 0, EL1
on page B2-231
ID_ISAR0_EL1 3 c0 0 c2 0 32 B2.65 ID_ISAR0_EL1, AArch32 Instruction Set Attribute
Register 0, EL1 on page B2-233
ID_ISAR1_EL1 3 c0 0 c2 1 32 B2.66 ID_ISAR1_EL1, AArch32 Instruction Set Attribute
Register 1, EL1 on page B2-235
ID_ISAR2_EL1 3 c0 0 c2 2 32 B2.67 ID_ISAR2_EL1, AArch32 Instruction Set Attribute
Register 2, EL1 on page B2-237
ID_ISAR3_EL1 3 c0 0 c2 3 32 B2.68 ID_ISAR3_EL1, AArch32 Instruction Set Attribute
Register 3, EL1 on page B2-239
ID_ISAR4_EL1 3 c0 0 c2 4 32 B2.69 ID_ISAR4_EL1, AArch32 Instruction Set Attribute
Register 4, EL1 on page B2-241
ID_ISAR5_EL1 3 c0 0 c2 5 32 B2.70 ID_ISAR5_EL1, AArch32 Instruction Set Attribute
Register 5, EL1 on page B2-243
ID_ISAR6_EL1 3 c0 0 c2 7 32 B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute
Register 6, EL1 on page B2-245
ID_MMFR0_EL1 3 c0 0 c1 4 32 B2.72 ID_MMFR0_EL1, AArch32 Memory Model Feature
Register 0, EL1 on page B2-246
ID_MMFR1_EL1 3 c0 0 c1 5 32 B2.73 ID_MMFR1_EL1, AArch32 Memory Model Feature
Register 1, EL1 on page B2-248
ID_MMFR2_EL1 3 c0 0 c1 6 32 B2.74 ID_MMFR2_EL1, AArch32 Memory Model Feature
Register 2, EL1 on page B2-250
ID_MMFR3_EL1 3 c0 0 c1 7 32 B2.75 ID_MMFR3_EL1, AArch32 Memory Model Feature
Register 3, EL1 on page B2-252
ID_MMFR4_EL1 3 c0 0 c2 6 32 B2.76 ID_MMFR4_EL1, AArch32 Memory Model Feature
Register 4, EL1 on page B2-254
ID_PFR0_EL1 3 c0 0 c1 0 32 B2.77 ID_PFR0_EL1, AArch32 Processor Feature Register 0,
EL1 on page B2-256
ID_PFR1_EL1 3 c0 0 c1 1 32 B2.78 ID_PFR1_EL1, AArch32 Processor Feature Register 1,
EL1 on page B2-258
ID_PFR2_EL1 3 c0 0 c3 4 32 B2.79 ID_PFR2_EL1, AArch32 Processor Feature Register 2,
EL1 on page B2-260
ID_AA64DFR0_EL1 3 c0 0 c5 0 64 B2.54 ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0,
EL1 on page B2-216
ID_AA64ISAR0_EL1 3 c0 0 c6 0 64 B2.56 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute
Register 0, EL1 on page B2-219
ID_AA64ISAR1_EL1 3 c0 0 c6 1 64 B2.57 ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute
Register 1, EL1 on page B2-221
ID_AA64MMFR0_EL1 3 c0 0 c7 0 64 B2.58 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature
Register 0, EL1 on page B2-222
ID_AA64MMFR1_EL1 3 c0 0 c7 1 64 B2.59 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature
Register 1, EL1 on page B2-224
B2 AArch64 system registers
B2.2 AArch64 architectural system register summary
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B2-129
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