ARM Cortex-A76 Core User Manual

Table B2-1 Registers with implementation defined bit fields (continued)
Name Op0 CRn Op1 CRm Op2 Width Description
ID_AA64MMFR2_EL1 3 c0 0 c7 2 64 B2.60 ID_AA64MMFR2_EL1, AArch64 Memory Model Feature
Register 2, EL1 on page B2-226
ID_AA64PFR0_EL1 3 c0 0 c4 0 64 B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature Register
0, EL1 on page B2-227
IFSR32_EL2 3 c5 4 c0 1 32
LORC_EL1 3 c10 0 c4 3 64 B2.80 LORC_EL1, LORegion Control Register, EL1
on page B2-261
LORID_EL1 3 c10 0 c4 7 64 B2.81 LORID_EL1, LORegion ID Register, EL1 on page B2-262
LORN_EL1 3 c10 0 c4 2 64 B2.82 LORN_EL1, LORegion Number Register, EL1
on page B2-263
MDCR_EL3 3 c1 6 c3 1 32 B2.83 MDCR_EL3, Monitor Debug Configuration Register, EL3
on page B2-264
MIDR_EL1 3 c0 0 c0 0 32 B2.84 MIDR_EL1, Main ID Register, EL1 on page B2-266
MPIDR_EL1 3 c0 0 c0 5 64 B2.85 MPIDR_EL1, Multiprocessor Affinity Register, EL1
on page B2-267
PAR_EL1 3 c7 0 c4 0 64 B2.86 PAR_EL1, Physical Address Register, EL1 on page B2-269
RVBAR_EL3 3 c12 6 c0 1 64 B2.89 RVBAR_EL3, Reset Vector Base Address Register, EL3
on page B2-272
REVIDR_EL1 3 c0 0 c0 6 32 B2.87 REVIDR_EL1, Revision ID Register, EL1 on page B2-270
SCTLR_EL1 3 c1 0 c0 0 32 B2.90 SCTLR_EL1, System Control Register, EL1
on page B2-273
SCTLR_EL2 3 c1 4 c0 0 32 B2.91 SCTLR_EL2, System Control Register, EL2
on page B2-275
SCTLR_EL12 3 c1 5 c0 0 32 B2.90 SCTLR_EL1, System Control Register, EL1
on page B2-273
SCTLR_EL3 3 c1 6 c0 0 32 B2.92 SCTLR_EL3, System Control Register, EL3
on page B2-276
TCR_EL1 3 c2 0 c0 2 64 B2.93 TCR_EL1, Translation Control Register, EL1
on page B2-278
TCR_EL2 3 c2 4 c0 2 64 B2.94 TCR_EL2, Translation Control Register, EL2
on page B2-279
TCR_EL3 3 c2 6 c0 2 64 B2.95 TCR_EL3, Translation Control Register, EL3
on page B2-280
TTBR0_EL1 3 c2 0 c0 0 64 B2.96 TTBR0_EL1, Translation Table Base Register 0, EL1
on page B2-281
TTBR0_EL2 3 c2 4 c0 0 64 B2.97 TTBR0_EL2, Translation Table Base Register 0, EL2
on page B2-282
TTBR0_EL3 3 c2 6 c0 0 64 B2.98 TTBR0_EL3, Translation Table Base Register 0, EL3
on page B2-283
TTBR1_EL1 3 c2 0 c0 1 64 B2.99 TTBR1_EL1, Translation Table Base Register 1, EL1
on page B2-284
B2 AArch64 system registers
B2.2 AArch64 architectural system register summary
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B2-130
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core