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Table B2-2 Other architecturally defined registers (continued)

Name Op0 CRn Op1 CRm Op2 Widt

Description

MDCR_EL2 3 c1 4 c1 1 32 Monitor Debug Configuration Register

MVFR0_EL1 3 c0 0 c3 0 32 AArch32 Media and VFP Feature Register 0

MVFR1_EL1 3 c0 0 c3 1 32 AArch32 Media and VFP Feature Register 1

MVFR2_EL1 3 c0 0 c3 2 32 AArch32 Media and VFP Feature Register 2

RMR_EL3 3 c12 6 c0 2 32 Reset Management Register

SCR_EL3 3 c1 6 c1 0 32 Secure Configuration Register

SDER32_EL3 3 c1 6 c1 1 32 AArch32 Secure Debug Enable Register

TCR_EL12 3 c2 5 c0 2 64 Translation Control Register (EL12)

TPIDR_EL0 3 c13 3 c0 2 64 EL0 Read/Write Software Thread ID Register

TPIDR_EL1 3 c13 0 c0 4 64 EL1 Software Thread ID Register

TPIDR_EL2 3 c13 4 c0 2 64 EL2 Software Thread ID Register

TPIDR_EL3 3 c13 6 c0 2 64 EL3 Software Thread ID Register

TPIDRRO_EL0 3 c13 3 c0 3 64 EL0 Read-Only Software Thread ID Register

TTBR0_EL12 3 c2 5 c0 0 64 Translation Table Base Register 0 (EL12)

TTBR1_EL12 3 c2 5 c0 1 64 Translation Table Base Register 1 (EL12)

VBAR_EL1 3 c12 0 c0 0 64 Vector Base Address Register (EL1)

VBAR_EL12 3 c12 5 c0 0 64 Vector Base Address Register (EL12)

VBAR_EL2 3 c12 4 c0 0 64 Vector Base Address Register (EL2)

VBAR_EL3 3 c12 6 c0 0 64 Vector Base Address Register (EL3)

VMPIDR_EL2 3 c0 4 c0 5 64 Virtualization Multiprocessor ID Register

VPIDR_EL2 3 c0 4 c0 0 32 Virtualization Core ID Register

B2 AArch64 system registers

B2.2 AArch64 architectural system register summary

reserved.

B2-133

Non-Confidential

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