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Table B2-2 Other architecturally defined registers (continued)

Name Op0 CRn Op1 CRm Op2 Widt

Description

CNTPS_TVAL_EL1 3 c14 7 c2 0 32 Counter-timer Physical Secure Timer TimerValue register

CNTV_CTL_EL0 3 c14 3 c3 1 32 Counter-timer Virtual Timer Control register

CNTV_CTL_EL02 3 c14 5 c3 1 32 Counter-timer Virtual Timer Control register

CNTV_CVAL_EL0 3 c14 3 c3 2 64 Counter-timer Virtual Timer CompareValue register

CNTV_CVAL_EL02 3 c14 5 c3 2 64 Counter-timer Virtual Timer CompareValue register

CNTV_TVAL_EL0 3 c14 3 c3 0 32 Counter-timer Virtual Timer TimerValue register

CNTV_TVAL_EL02 3 c14 5 c3 0 32 Counter-timer Virtual Timer TimerValue register

CNTVCT_EL0 3 c14 3 c0 2 64 Counter-timer Virtual Count register

CNTVOFF_EL2 3 c14 4 c0 3 64 Counter-timer Virtual Offset register

CONTEXTIDR_EL1 3 c13 0 c0 1 32 Context ID Register (EL1)

CONTEXTIDR_EL12 3 c13 5 c0 1 32 Context ID Register (EL12)

CONTEXTIDR_EL2 3 c13 4 c0 1 32 Context ID Register (EL2)

CPACR_EL12 3 c1 5 c0 2 32 Architectural Feature Access Control Register

CPTR_EL3 3 c1 6 c1 2 32 Architectural Feature Trap Register (EL3)

DACR32_EL2 3 c3 4 c0 0 32 Domain Access Control Register

ESR_EL12 3 c5 5 c2 0 32 Exception Syndrome Register (EL12)

FAR_EL1 3 c6 0 c0 0 64 Fault Address Register (EL1)

FAR_EL12 3 c6 5 c0 0 64 Fault Address Register (EL12)

FAR_EL2 3 c6 4 c0 0 64 Fault Address Register (EL2)

FAR_EL3 3 c6 6 c0 0 64 Fault Address Register (EL3)

FPEXC32_EL2 3 c5 4 c3 0 32 Floating-point Exception Control register

HPFAR_EL2 3 c6 4 c0 4 64 Hypervisor IPA Fault Address Register

HSTR_EL2 3 c1 4 c1 3 32 Hypervisor System Trap Register

ID_AA64AFR0_EL1 3 c0 0 c5 4 64 AArch64 Auxiliary Feature Register 0

ID_AA64AFR1_EL1 3 c0 0 c5 5 64 AArch64 Auxiliary Feature Register 1

ID_AA64DFR1_EL1 3 c0 0 c5 1 64 AArch64 Debug Feature Register 1

ID_AA64PFR1_EL1 3 c0 0 c4 1 64 AArch64 Core Feature Register 1

ISR_EL1 3 c12 0 c1 0 32 Interrupt Status Register

LOREA_EL1 3 c10 0 c4 1 64 LORegion End Address Register

LORSA_EL1 3 c10 0 c4 0 64 LORegion Start Address Register

MAIR_EL1 3 c10 0 c2 0 64 Memory Attribute Indirection Register (EL1)

MAIR_EL12 3 c10 5 c2 0 64 Memory Attribute Indirection Register (EL12)

MAIR_EL2 3 c10 4 c2 0 64 Memory Attribute Indirection Register (EL2)

MAIR_EL3 3 c10 6 c2 0 64 Memory Attribute Indirection Register (EL3)

B2 AArch64 system registers

B2.2 AArch64 architectural system register summary

reserved.

B2-132

Non-Confidential

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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core