ARM Cortex-A76 Core User Manual

Table D6-1 Memory-mapped PMU register summary (continued)
Offset Name Type Description
0x418-0x478
- - Reserved
0x47C
PMCCFILTR_EL0 RW
Performance Monitor Cycle Count Filter
Register
0x600
PMPCSSR_LO RO D7.2 PMPCSSR, Snapshot Program
Counter Sample Register on page D7-473
0x604
PMPCSSR_HI RO
0x608
PMCIDSSR RO D7.3 PMCIDSSR, Snapshot
CONTEXTIDR_EL1 Sample Register
on page D7-474
0x60C
PMCID2SSR RO D7.4 PMCID2SSR, Snapshot
CONTEXTIDR_EL2 Sample Register
on page D7-475
0x610
PMSSSR RO D7.5 PMSSSR, PMU Snapshot Status
Register on page D7-476
0x614
PMOVSSR RO D7.6 PMOVSSR, PMU Overflow Status
Snapshot Register on page D7-477
0x618
PMCCNTSR_LO RO D7.7 PMCCNTSR, PMU Cycle Counter
Snapshot Register on page D7-478
0x61C
PMCCNTSR_HI RO
0x620+ 4×n PMEVCNTSRn RO D7.8 PMEVCNTSRn, PMU Cycle Counter
Snapshot Registers 0-5 on page D7-479
0x6F0
PMSSCR WO D7.9 PMSSCR, PMU Snapshot Capture
Register on page D7-480
0xC00
PMCNTENSET_EL0 RW
Performance Monitor Count Enable Set
Register
0xC04-0xC1C
- - Reserved
0xC20
PMCNTENCLR_EL0 RW
Performance Monitor Count Enable Clear
Register
0xC24-0xC3C
- - Reserved
0xC40
PMINTENSET_EL1 RW
Performance Monitor Interrupt Enable Set
Register
0xC44-0xC5C
- - Reserved
0xC60
PMINTENCLR_EL1 RW
Performance Monitor Interrupt Enable
Clear Register
0xC64-0xC7C
- - Reserved
0xC80
PMOVSCLR_EL0 RW
Performance Monitor Overflow Flag Status
Register
0xC84-0xC9C
- - Reserved
0xCA0
PMSWINC_EL0 WO
Performance Monitor Software Increment
Register
D6 Memory-mapped PMU registers
D6.1 Memory-mapped PMU register summary
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
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D6-457
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core