ARM Cortex-A76 Core User Manual

Table D6-1 Memory-mapped PMU register summary (continued)
Offset Name Type Description
0xCA4-0xCBC
- - Reserved
0xCC0
PMOVSSET_EL0 RW Performance Monitor Overflow Flag Status
Set Register
0xCC4-0xDFC
- - Reserved
0xE00
PMCFGR RO D6.2 PMCFGR, Performance Monitors
Configuration Register on page D6-460
0xE04
PMCR_EL0 RW
Performance Monitors Control Register.
This register is distinct from the
PMCR_EL0 system register. It does not
have the same value.
0xE08-0xE1C
- - Reserved
0xE20
PMCEID0 RO D5.2 PMCEID0_EL0, Performance
Monitors Common Event Identification
Register 0, EL0 on page D5-448
0xE24
PMCEID1 RO D5.3 PMCEID1_EL0, Performance
Monitors Common Event Identification
Register 1, EL0 on page D5-451
0xE28
PMCEID2 RO
0xE2C
PMCEID3 RO
0xFA4
- - Reserved
0xFA8
PMDEVAFF0 RO B2.85 MPIDR_EL1, Multiprocessor
Affinity Register, EL1 on page B2-267
0xFAC
PMDEVAFF1 RO B2.85 MPIDR_EL1, Multiprocessor
Affinity Register, EL1 on page B2-267
0xFB8
PMAUTHSTATUS RO
Performance Monitor Authentication Status
Register
0xFBC
PMDEVARCH RO Performance Monitor Device Architecture
Register
0xFC0-0xFC8
- - Reserved
0xFCC
PMDEVTYPE RO
Performance Monitor Device Type Register
0xFD0
PMPIDR4 RO D6.11 PMPIDR4, Performance Monitors
Peripheral Identification Register 4
on page D6-469
0xFD4
PMPIDR5 RO D6.12 PMPIDRn, Performance Monitors
Peripheral Identification Register 5-7
on page D6-470
0xFD8
PMPIDR6 RO
0xFDC
PMPIDR7 RO
0xFE0
PMPIDR0 RO D6.7 PMPIDR0, Performance Monitors
Peripheral Identification Register 0
on page D6-465
D6 Memory-mapped PMU registers
D6.1 Memory-mapped PMU register summary
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
D6-458
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core