ARM Cortex-A76 Core - Page 459

Table D6-1 Memory-mapped PMU register summary (continued)
Offset Name Type Description
0xFE4
PMPIDR1 RO D6.8 PMPIDR1, Performance Monitors
Peripheral Identification Register 1
on page D6-466
0xFE8
PMPIDR2 RO D6.9 PMPIDR2, Performance Monitors
Peripheral Identification Register 2
on page D6-467
0xFEC
PMPIDR3 RO D6.10 PMPIDR3, Performance Monitors
Peripheral Identification Register 3
on page D6-468
0xFF0
PMCIDR0 RO D6.3 PMCIDR0, Performance Monitors
Component Identification Register 0
on page D6-461
0xFF4
PMCIDR1 RO D6.4 PMCIDR1, Performance Monitors
Component Identification Register 1
on page D6-462
0xFF8
PMCIDR2 RO D6.5 PMCIDR2, Performance Monitors
Component Identification Register 2
on page D6-463
0xFFC
PMCIDR3 RO D6.6 PMCIDR3, Performance Monitors
Component Identification Register 3
on page D6-464
D6 Memory-mapped PMU registers
D6.1 Memory-mapped PMU register summary
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