ARM Cortex-A76 Core User Manual

D2.1 AArch64 debug register summary
These registers, listed in the following table, are accessed by the MRS and MSR instructions in the order of
Op0, CRn, Op1, CRm, Op2.
See D3.1 Memory-mapped debug register summary on page D3-416 for a complete list of registers
accessible from the external debug interface. The 64-bit registers cover two addresses on the external
memory interface. For those registers not described in this chapter, see the Arm
®
Architecture Reference
Manual Armv8, for Armv8-A architecture profile.
Table D2-1 AArch64 debug register summary
Name Type Reset Width Description
OSDTRRX_EL1 RW
0x00000000
32 Debug Data Transfer Register, Receive, External View
DBGBVR0_EL1 RW - 64 Debug Breakpoint Value Register 0
DBGBCR0_EL1 RW UNK 32 D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
on page D2-408
DBGWVR0_EL1 RW - 64 Debug Watchpoint Value Register 0
DBGWCR0_EL1 RW UNK 32 D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
on page D2-412
DBGBVR1_EL1 RW - 64 Debug Breakpoint Value Register 1
DBGBCR1_EL1 RW UNK 32 D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
on page D2-408
DBGWVR1_EL1 RW - 64 Debug Watchpoint Value Register 1
DBGWCR1_EL1 RW UNK 32 D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
on page D2-412
MDCCINT_EL1 RW
0x00000000
32 Monitor Debug Comms Channel Interrupt Enable Register
MDSCR_EL1 RW - 32
DBGBVR2_EL1 RW - 64 Debug Breakpoint Value Register 2
DBGBCR2_EL1 RW UNK 32 D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
on page D2-408
DBGWVR2_EL1 RW - 64 Debug Watchpoint Value Register 2
DBGWCR2_EL1 RW UNK 32 D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
on page D2-412
OSDTRTX_EL1 RW - 32 Debug Data Transfer Register, Transmit, External View
DBGBVR3_EL1 RW - 64 Debug Breakpoint Value Register 3
DBGBCR3_EL1 RW UNK 32 D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
on page D2-408
DBGWVR3_EL1 RW - 64 Debug Watchpoint Value Register 3
DBGWCR3_EL1 RW UNK 32 D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
on page D2-412
DBGBVR4_EL1 RW - 64 Debug Breakpoint Value Register 4
DBGBCR4_EL1 RW UNK 32 D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
on page D2-408
D2 AArch64 debug registers
D2.1 AArch64 debug register summary
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core