ARM Cortex-A76 Core User Manual

0x1 ICV_EOIR0_EL1 and ICV_EOIR1_EL1 provide priority drop functionality only.
ICV_DIR provides interrupt deactivation functionality.
VCBPR, [0]
Common Binary Point Register. Controls whether the same register is used for interrupt
preemption of both virtual Group 0 and virtual Group 1 interrupts. The possible values are:
0 ICV_BPR0_EL1 determines the preemption group for virtual Group 0 interrupts
only.
ICV_BPR1_EL1 determines the preemption group for virtual Group 1 interrupts.
1 ICV_BPR0_EL1 determines the preemption group for both virtual Group 0 and
virtual Group 1 interrupts.
Reads of ICV_BPR1_EL1 return ICV_BPR0_EL1 plus one, saturated to 111. Writes
to ICV_BPR1_EL1 are IGNORED.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm
®
Generic Interrupt Controller Architecture Specification.
B4 GIC registers
B4.17 ICV_CTLR_EL1, Interrupt Controller Virtual Control Register, EL1
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B4-334
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core