ARM Cortex-A76 Core

A.3 Armv8 Debug UNPREDICTABLE behaviors
This section describes the behavior that the Cortex-A76 core implements when:
• A topic has multiple options.
• The behavior differs from either or both of the Options and Preferences behaviors.
Note
This section does not describe the behavior when a topic only has a single option and the core
implements the preferred behavior.
Table A-1 Armv8 Debug UNPREDICTABLE behaviors
Scenario Behavior
A32 BKPT instruction with condition code not
AL
The core implements the following preferred option:
• Executed unconditionally.
Address match breakpoint match only on second
halfword of an instruction
The core generates a breakpoint on the instruction if CPSR.IL=0. In the case of
CPSR.IL=1, the core does not generate a breakpoint exception.
Address matching breakpoint on A32 instruction
with DBGBCRn.BAS=1100
The core implements the following option:
• Does match if CPSR.IL=0.
Address match breakpoint match on T32
instruction at DBGBCRn+2 with
DBGBCRn.BAS=1111
The core implements the following option:
• Does match.
Link to non-existent breakpoint or breakpoint that
is not context-aware
The core implements the following option:
• No Breakpoint or Watchpoint debug event is generated, and the LBN field of
the linker reads UNKNOWN.
DBGWCRn_EL1.MASK!=00000 and
DBGWCRn_EL1.BAS!=11111111
The core behaves as indicated in the sole Preference:
• DBGWCRn_EL1.BAS is ignored and treated as if 0x11111111.
Address match breakpoint with
DBGBCRn_EL1.BAS=0000
The core implements the following option:
• As if disabled.
DBGWCRn_EL1.BAS specifies a non-
contiguous set of bytes within a double-word
The core implements the following option:
• A Watchpoint debug event is generated for each byte.
A32 HLT instruction with condition code not AL The core implements the following option:
• Executed unconditionally.
Execute instruction at a given EL when the
corresponding EDECCR bit is 1 and Halting is
allowed
The core behaves as follows:
• Generates debug event and Halt no later than the instruction following the next
Context Synchronization operation (CSO) excluding ISB instruction.
H > N or H = 0 at Non-secure EL1 and EL0,
including value read from PMCR_EL0.N
The core implements:
• A simple implementation where all of HPMN[4:0] are implemented, and In
Non-secure EL1 and EL0:
— If H > N then M = N.
— If H = 0 then M = 0.
H > N or H = 0: value read back in
MDCR_EL2.HPMN
The core implements:
• A simple implementation where all of HPMN[4:0] are implemented and for
reads of MDCR_EL2.HPMN, return H.
A Cortex
®
-A76 Core AArch32 unpredictable behaviors
A.3 Armv8 Debug UNPREDICTABLE behaviors
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