ARM Cortex-A76 Core User Manual

A.2 Load/Store accesses crossing page boundaries
The Cortex-A76 core implements a set of behaviors for load or store accesses that cross page boundaries.
Crossing a page boundary with different memory types or shareability attributes
The Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile, states that a
memory access from a load or store instruction that crosses a page boundary to a memory
location that has a different memory type or shareability attribute results in CONSTRAINED
UNPREDICTABLE behavior.
Crossing a 4KB boundary with a Device access
The Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile, states that a
memory access from a load or store instruction to Device memory that crosses a 4KB boundary
results in CONSTRAINED UNPREDICTABLE behavior.
Implementation (for both page boundary specifications)
For an access that crosses a page boundary, the Cortex-A76 core implements the following
behaviors:
• Store crossing a page boundary:
— No alignment fault.
— The access is split into two stores.
— Each store uses the memory type and shareability attributes associated with its own
address.
• Load crossing a page boundary (Device to Device and Normal to Normal):
— No alignment fault.
— The access is split into two loads.
— Each load uses the memory type and shareability attributes associated with its own
address.
• Load crossing a page boundary (Device to Normal and Normal to Device):
— The instruction will generate an alignment fault.
A Cortex
®
-A76 Core AArch32 unpredictable behaviors
A.2 Load/Store accesses crossing page boundaries
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core