A.2 Load/Store accesses crossing page boundaries
The Cortex-A76 core implements a set of behaviors for load or store accesses that cross page boundaries.
Crossing a page boundary with different memory types or shareability attributes
The Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile, states that a
memory access from a load or store instruction that crosses a page boundary to a memory
location that has a different memory type or shareability attribute results in CONSTRAINED
UNPREDICTABLE behavior.
Crossing a 4KB boundary with a Device access
The Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile, states that a
memory access from a load or store instruction to Device memory that crosses a 4KB boundary
results in CONSTRAINED UNPREDICTABLE behavior.
Implementation (for both page boundary specifications)
For an access that crosses a page boundary, the Cortex-A76 core implements the following
behaviors:
• Store crossing a page boundary:
— No alignment fault.
— The access is split into two stores.
— Each store uses the memory type and shareability attributes associated with its own
address.
• Load crossing a page boundary (Device to Device and Normal to Normal):
— No alignment fault.
— The access is split into two loads.
— Each load uses the memory type and shareability attributes associated with its own
address.
• Load crossing a page boundary (Device to Normal and Normal to Device):
— The instruction will generate an alignment fault.
A Cortex
®
-A76 Core AArch32 unpredictable behaviors
A.2 Load/Store accesses crossing page boundaries
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
Appx-A-593
Non-Confidential
To Next Page
Loading...
