ARM Cortex-A76 Core User Manual

Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus
Figure 1 Key to timing diagram conventions
Signals
The signal conventions are:
Signal level
The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW.
Asserted means:
• HIGH for active-HIGH signals.
• LOW for active-LOW signals.
Lowercase n
At the start or end of a signal name denotes an active-LOW signal.
Additional reading
This book contains information that is specific to this product. See the following documents for other
relevant information.
Arm publications
• Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile (DDI 0487).
• Arm
®
Cortex
®
-A76 Core Cryptographic Extension Technical Reference Manual (100801).
• Arm
®
Cortex
®
-A76 Core Configuration and Sign-off Guide (100799).
• Arm
®
Cortex
®
-A76 Core Integration Manual (100800).
• Arm
®
DynamIQ
™
Shared Unit Integration Manual (100455).
• Arm
®
DynamIQ
™
Shared Unit Technical Reference Manual (100453).
• Arm
®
DynamIQ
™
Shared Unit Configuration and Sign-off Guide (100454).
• Arm
®
CoreSight
™
ELA-500 Embedded Logic Analyzer Technical Reference Manual
(100127).
• AMBA
®
AXI
™
and ACE
™
Protocol Specification AXI3
™
, AXI4
™
, and AXI4-Lite
™
, ACE and
ACE-Lite
™
(IHI 0022).
• AMBA
®
APB Protocol Version 2.0 Specification (IHI 0024).
• Arm
®
AMBA
®
5 CHI Architecture Specification (IHI 0050).
• Arm
®
CoreSight
™
Architecture Specification v3.0 (IHI 0029).
• Arm
®
Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2 (IHI 0031).
• AMBA
®
4 ATB Protocol Specification (IHI 0032).
• Arm
®
Generic Interrupt Controller Architecture Specification (IHI 0069).
• Arm
®
Embedded Trace Macrocell Architecture Specification ETMv4 (IHI 0064).
• AMBA
®
Low Power Interface Specification Arm
®
Q-Channel and P-Channel Interfaces (IHI
0068).
• Arm
®
Reliability, Availability, and Serviceability (RAS) Specification, Armv8, for the Armv8-
A architecture profile (DDI 0587A).
Preface
Additional reading
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
19
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core