ARM Cortex-A76 Core User Manual

0b01 L2 Data RAM.
0b10 TQ Data RAM.
0b11 CHI Slave Error.
L1 Data
Cache
Indicates which array detected the error. The possible values are:
0b00 LS0 copy of Tag RAM.
0b01 LS1 copy of Tag RAM.
0b10 LS Tag RAM.
L1 Instruction
Cache
Indicates which array that detected the error, Data Array has higher priority.
The possible values are:
0b0 Tag.
0b1 Data.
UNIT, [3:0]
Indicates the unit which detected the error. The possible values are:
0b1000 L2 Cache.
0b0100 L1 Data Cache.
0b0010 L2 TLB.
0b0001 L1 Instruction Cache.
Configurations
ERR0MISC0 resets to [63:32] is 0x00000000, [31:0] is UNKNOWN.
This register is accessible from the following registers when ERRSELR.SEL==0:
• B2.41 ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1
on page B2-201.
B3 Error system registers
B3.5 ERR0MISC0, Error Record Miscellaneous Register 0
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
B3-300
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core