Table B-3 Differences between Issue 0100-00 and Issue 0200-00
Change Location Affects
Fixed typographical errors.
Throughout document -
Added information for L1 Prefetch History
Table.
Table A8-1 Cache protection behavior on page A8-103 r2p0
Updated ATCR_EL12 description.
Table B2-3 AArch64 implementation defined registers on page B2-134 r2p0
Updated reset value for
ID_AA64PFR0_EL1.
B2.4 AArch64 registers by functional group on page B2-136 r2p0
Updated reset value for ID_PFR0_EL1.
B2.4 AArch64 registers by functional group on page B2-136 r2p0
Added new register ID_PFR2_EL1. B2.4 AArch64 registers by functional group on page B2-136
B2.79 ID_PFR2_EL1, AArch32 Processor Feature Register 2, EL1
on page B2-260
r2p0
Updated reset value for MIDR_EL1. B2.4 AArch64 registers by functional group on page B2-136
B2.84 MIDR_EL1, Main ID Register, EL1 on page B2-266
r2p0
Added CSV2 and CSV3 fields to register.
B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1
on page B2-227
r2p0
Added CSV2 field to register.
B2.77 ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1
on page B2-256
r2p0
Added TRCVMIDCCTLR0 register
description.
D9.76 TRCVMIDCCTLR0, Virtual context identifier Comparator Control
Register 0 on page D9-588
r2p0
Table B-4 Differences between Issue 0200-00 and Issue 0300-00
Change Location Affects
Fixed typographical errors.
Throughout document -
Added new register ID_AA64PFR1_EL1.
B2.62 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1
on page B2-229
r3p0
Updated reset value for ID_PFR2_EL1.
B2.4 AArch64 registers by functional group on page B2-136 r3p0
Updated reset value for MIDR_EL1.
B2.4 AArch64 registers by functional group on page B2-136 r3p0
Updated reset value for TRCIDR1.
D9.1 ETM register summary on page D9-495 r3p0
Added SSBS field to ID_AA64PFR1_EL1. B2.62 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1
on page B2-229
r3p0
B Revisions
B.1 Revisions
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
Appx-B-601
Non-Confidential
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