ARM Cortex-A76 Core User Manual

Table B-3 Differences between Issue 0100-00 and Issue 0200-00
Change Location Affects
Fixed typographical errors.
Throughout document -
Added information for L1 Prefetch History
Table.
Table A8-1 Cache protection behavior on page A8-103 r2p0
Updated ATCR_EL12 description.
Table B2-3 AArch64 implementation defined registers on page B2-134 r2p0
Updated reset value for
ID_AA64PFR0_EL1.
B2.4 AArch64 registers by functional group on page B2-136 r2p0
Updated reset value for ID_PFR0_EL1.
B2.4 AArch64 registers by functional group on page B2-136 r2p0
Added new register ID_PFR2_EL1. B2.4 AArch64 registers by functional group on page B2-136
B2.79 ID_PFR2_EL1, AArch32 Processor Feature Register 2, EL1
on page B2-260
r2p0
Updated reset value for MIDR_EL1. B2.4 AArch64 registers by functional group on page B2-136
B2.84 MIDR_EL1, Main ID Register, EL1 on page B2-266
r2p0
Added CSV2 and CSV3 fields to register.
B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1
on page B2-227
r2p0
Added CSV2 field to register.
B2.77 ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1
on page B2-256
r2p0
Added TRCVMIDCCTLR0 register
description.
D9.76 TRCVMIDCCTLR0, Virtual context identifier Comparator Control
Register 0 on page D9-588
r2p0
Table B-4 Differences between Issue 0200-00 and Issue 0300-00
Change Location Affects
Fixed typographical errors.
Throughout document -
Added new register ID_AA64PFR1_EL1.
B2.62 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1
on page B2-229
r3p0
Updated reset value for ID_PFR2_EL1.
B2.4 AArch64 registers by functional group on page B2-136 r3p0
Updated reset value for MIDR_EL1.
B2.4 AArch64 registers by functional group on page B2-136 r3p0
Updated reset value for TRCIDR1.
D9.1 ETM register summary on page D9-495 r3p0
Added SSBS field to ID_AA64PFR1_EL1. B2.62 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1
on page B2-229
r3p0
B Revisions
B.1 Revisions
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
Appx-B-601
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core